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rf agile transceiver data sheet AD9361 rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com feature s rf 2 2 transceiver with integrated 12 - bit dacs and adcs band : 70 mhz to 6.0 ghz supports tdd and fdd operation tunable channel bandwidth : <200 khz to 56 mhz dual receivers: 6 differential or 12 single - ended inputs superior receiver sensitivity with a no i se figure of 2 db at 800 mhz local oscillator (lo) r x gain control real - time monitor and control signals for manual gain independent automatic gain control du al transmitters: 4 differential outputs highly linear broadband transmitter t x evm: ?40 db tx noise: ? 157 dbm/hz noise floor tx monitor: 66 db dynamic range with 1 db accuracy integrated fractional - n synthesizer s 2. 4 hz maximum lo step size multichip synchronization cmos/lvds digital interface applications point to point communication systems femtocell/picocell/microcell base stations general - purpose radio systems functional block dia gram figure 1 . general description the AD9361 is a high performance, highly integrated radio frequency ( rf ) agile transceiver? designed for use in 3g and 4g base station applications. its programmability and wideband capability mak e it ideal for a broad range of transceiver applications. the device combines a rf front end with a flexible mixed - signal baseband section and integrated frequency synthesizers, simplifying design - in by providing a configurable digital interface to a proce ssor. the AD9361 operates in the 70 mhz to 6.0 ghz range, covering most licensed and unlicensed bands. channel bandwidths from less than 200 khz to 56 mhz are supported. the two independent direct conversion receivers have state - of - the - art noise figure and linearity. each receive (rx) subsystem includes independent automatic gain control (agc), dc offset correction , quadrature correction, and digital filtering, thereby eliminating t he need for these functions in the digital baseband. the AD9361 also has flexible manual gain modes that can be externally controlled. two high dynamic range adcs per channel digitize the received i and q signals and pass them through configurable decimation filters and 128 - tap finite impulse response ( fir ) filters to produce a 12- bit output signal at the appropriate sample rate. the transmitters use a direct conversion architecture t hat achieves h igh modulation accuracy with ultralow noise . this transmitter design produces a best in class tx evm of < ? 40 db, allowing s ignificant system margin for the external pa selection. the on - board transmit (tx) power monitor can be used as a power detector, enabling highly accurate tx power measurements. the fully integrated phase - locked loops (plls) provide low power fractional - n frequency synthesis for all receive and transmit channels. channel isolation , demanded by frequency division duplex (fdd) systems , is integrated into the design. all vco and loop filter components are integrated. the core of the AD9361 can be powered directly from a 1.3 v regulator. the ic is controlled via a standard 4 - wir e serial port and four real - time i/ o control pins. comprehensive power - down mode s are included to minimize power consumption during normal use. the AD9361 is packaged in a 10 mm 10 mm, 144- ball chip scale package ball grid array (csp_bga). AD9361 rx1b_p, rx1b_n p1_[d11:d0]/ rx_[d5:d0] p0_[d11:d0]/ tx_[d5:d0] radio switching notes 1. spi, ctrl, p0_[d11:d0]/tx_[d5:d0], p1_[d11:d0]/rx_[d5:d0], and radio switching contain multiple pins. rx1a_p, rx1a_n rx1c_p, rx1c_n rx2b_p, rx2b_n rx2a_p, rx2a_n rx2c_p, rx2c_n tx_mon1 data interface rx lo tx lo tx1a_p, tx1a_n tx1b_p, tx1b_n tx_mon2 tx2a_p, tx2a_n tx2b_p, tx2b_n ctrl auxdacx xtalp xtaln auxadc ctrl spi dac dac gpo plls dac adc clk_out dac adc adc 10453-001
AD9361 data sheet rev. d | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 current consumption vdd_interface .................................. 8 current consumption vddd1p3_dig and vddax (combination of all 1.3 v supplies) ......................................... 10 absolute maximum ratings ..................................................... 15 reflow profile .............................................................................. 15 thermal resistance .................................................................... 15 esd caution ................................................................................ 15 pin configuration and function descriptions ........................... 16 typical performance characteristics ........................................... 20 800 mhz frequency band ......................................................... 20 2.4 ghz frequency band .......................................................... 25 5.5 ghz frequency band .......................................................... 29 theory of operation ...................................................................... 33 general ......................................................................................... 33 receiver ........................................................................................ 33 transmitter .................................................................................. 33 clock input options .................................................................. 33 synthesi zers ................................................................................. 34 digital data interface ................................................................. 34 enable state machine ................................................................. 34 spi interface ................................................................................ 35 control pins ................................................................................ 35 gpo pins (gpo_3 to gpo_0) ................................................. 35 auxiliary converters .................................................................. 35 powering the AD9361 ................................................................ 35 packaging and ordering information ......................................... 36 outline dimensions ................................................................... 36 ordering guide .......................................................................... 36 revision history 11/13 rev. c to rev. d changes to ordering guide .......................................................... 36 9/ 13 revision c : initial version
data sheet AD9361 rev. d | page 3 of 36 specifications electrical characteristics at vdd_gpo = 3.3 v, vdd_interface = 1.8 v, and all other vdd x pins = 1.3 v, t a = 25 c , unless otherwise noted. table 1. parameter 1 symbol min typ max unit test conditions/ comments receivers , general center frequency 70 6000 mhz gain minimum 0 db maximum 74.5 db at 800 mhz 73.0 db at 2300 mhz ( rx1a, rx2a ) 72.0 db at 2300 mhz ( rx1b, rx1c, rx2b, rx2c ) 65.5 db at 5500 mhz ( rx1a, rx2a ) gain step 1 db rec eived signal strength indicator rssi range 100 db accuracy 2 db receivers, 800 mhz noise figure nf 2 db maximum rx gain third - order input intermodulation intercept point iip3 ?18 dbm maximum rx gain second - order input intermodulation intercept point iip2 40 dbm maximum rx gain local oscillator (lo) leakage ?122 dbm at rx front - end input quadrature gain error 0.2 % phase error 0.2 degrees modulation accuracy (evm) ?42 db 19.2 mhz reference clock input s 11 ?10 db rx1 to rx2 isolation rx1a to rx2a, rx1 c to rx2 c 70 db rx1 b to rx2 b 55 db rx2 to rx1 isolation rx2a to rx1a, rx2 c to rx1 c 70 db rx2 b to rx1 b 55 db receivers, 2.4 ghz noise figure nf 3 db maximum rx gain third - order input intermodulation intercept point iip3 ?14 dbm maximum rx gain second - order input intermodulation intercept point iip2 45 dbm maximum rx gain local oscillator (lo) leakage ?110 dbm at receiver front - end input quadrature gain error 0.2 % phase error 0.2 degrees modulation accuracy (evm) ?42 db 40 mhz reference clock input s 11 ?10 db rx1 to rx2 isolation rx1a to rx2a, rx1 c to rx2 c 65 db rx1 b to rx2 b 50 db rx2 to rx1 isolation rx2a to rx1a, rx2 c to rx1 c 65 db rx2 b to rx1 b 50 db
AD9361 data sheet rev. d | page 4 of 36 parameter 1 symbol min typ max unit test conditions/ comments receivers, 5.5 ghz noise figure nf 3.8 db maximum rx gain third - order input intermodulation intercept point iip3 ? 17 dbm maximum rx gain second - order input intermodulation intercept point iip2 42 dbm maximum rx gain local oscillator (lo) leakage ? 95 dbm at rx front - end input quadrature gain error 0.2 % phase error 0.2 degrees modulation accuracy (evm) ? 37 db 40 mhz reference clock (doubled internally for rf synthesizer ) input s 11 ? 10 db rx1 a to rx2 a isolation 52 db rx2 a to rx1 a isolation 52 db transmitters general center frequency 70 6000 mhz power control range 90 db power control resolution 0.25 db transmitters, 800 mhz output s 22 ?10 db maximum output power 8 dbm 1 mhz tone into 50 ? load modulation accuracy (evm) ?40 db 19.2 mhz reference clock third - order output intermodulation intercept point oip3 23 dbm carrier leakage ?50 dbc 0 db attenuation ?32 dbc 40 db attenuation noise floor ?157 dbm/hz 90 mhz offset isolation tx1 to tx2 50 db tx2 to tx1 50 db transmitters, 2.4 ghz output s 22 ?10 db maximum output power 7.5 dbm 1 mhz tone into 50 ? load modulation accuracy (evm) ?40 db 40 mhz reference clock third - order output intermod - ulation intercept point oip3 19 dbm carrier leakage ?50 dbc 0 db attenuation ?32 dbc 40 db attenuation noise floor ?156 dbm/hz 90 mhz offset isolation tx1 to tx2 50 db tx2 to tx1 50 db transmitters, 5.5 ghz output s 22 ?10 db maximum output power 6.5 dbm 7 mhz tone into 50 ? load modulation accuracy (evm) ?36 db 40 mhz reference clock (doubled internally for rf synthesizer ) third - order output intermodulation intercept point oip3 17 dbm carrier leakage ?50 dbc 0 db attenuation ?30 dbc 40 db attenuation noise floor ?151.5 dbm/hz 90 mhz offset isolation tx1 to tx2 50 db tx2 to tx1 50 db
data sheet AD9361 rev. d | page 5 of 36 parameter 1 symbol min typ max unit test conditions/ comments tx monitor inputs (tx_mon1, tx_mon2) maximum input level 4 dbm dynamic range 66 db accuracy 1 db lo synthesizer lo frequency step 2.4 hz 2.4 ghz, 40 mhz reference clock integrated phase noise 800 mhz 0. 13 rms 100 hz to 100 mhz, 30.72 mhz reference clock (doubled internally for rf synthesizer) 2.4 ghz 0.37 rms 100 hz to 100 mhz, 40 mhz reference clock 5.5 ghz 0.59 rms 100 hz to 100 mhz, 40 mhz reference clock (doubled internally for rf synthesizer ) reference clock (ref_clk) ref_clk is either the input to the xtalp/xtaln pins or a line directly to the xtaln pin input frequency range 19 50 mhz crystal input 10 80 mhz external oscillator signal level 1.3 v p - p ac - coupled external oscillator auxiliary converters adc resolution 12 bits input voltage minimum 0.05 v maximum vdda1p3 _bb ? 0.05 v dac resolution 10 bits output voltage minimum 0.5 v maximum vdd_gpo ? 0.3 v output current 10 ma digital specifications (cmos) logic inputs input voltage high vdd_interface 0.8 vdd_interface v low 0 vdd_interface 0.2 v input current high ?10 +10 a low ?10 +10 a logic outputs output voltage high vdd_interface 0.8 v low vdd_interface 0.2 v digital specifications (lvds) logic inputs input voltage range 825 1575 mv each differential input in the pair input differential voltage threshold ?100 +100 mv receiver differential input impedance 100 ?
AD9361 data sheet rev. d | page 6 of 36 parameter 1 symbol min typ max unit test conditions/ comments logic outputs output voltage high 1375 mv low 1025 mv output differential voltage 150 mv programmable in 75 mv steps output offset voltage 1200 mv general - purpose outputs output voltage high vdd_gpo 0.8 v low vdd_gpo 0.2 v output current 10 ma spi timing vdd_interface = 1.8 v spi_clk period t cp 20 ns pulse width t mp 9 ns spi_enb setup to first spi_clk rising edge t sc 1 ns last spi_clk falling edge to spi_enb hold t hc 0 ns spi_di data input setup to spi_clk t s 2 ns data input hold to spi_clk t h 1 ns spi_clk rising edge to output data delay 4 - wire mode t co 3 8 ns 3 - wire mode t co 3 8 ns bus turnaround time, read t hzm t h t co (max) ns after bbp drives the last address bit bus turnaround time, read t hzs 0 t co (max) ns after AD9361 drives the last data bit digital data timing (cmos), vdd_interface = 1.8 v data_clk clock period t cp 16.276 ns 61.44 mhz data_clk and fb_clk pulse width t mp 45% of t cp 55% of t cp ns tx data tx_frame, p0_d, and p1_d setup to fb_clk t stx 1 ns hold to fb_clk t htx 0 ns data_clk to data bus output delay t ddrx 0 1.5 ns data_clk to rx_frame delay t dddv 0 1.0 ns pulse width enable t enpw t cp ns txnrx t txnrxpw t cp ns fdd independent ensm mode txnrx setup to enable t txnrxsu 0 ns tdd ensm mode bus turnaround time before rx t rpre 2 t cp ns tdd mode after rx t rpst 2 t cp ns tdd mode capacitive load 3 pf capacitive input 3 pf
data sheet AD9361 rev. d | page 7 of 36 parameter 1 symbol min typ max unit test conditions/ comments digital data timing (cmos), vdd_interface = 2.5 v data_clk clock period t cp 16.276 ns 61.44 mhz data_clk and fb_clk pulse width t mp 45% of t cp 55% of t cp ns tx data tx_frame, p0_d, and p1_d setup to fb_clk t stx 1 ns hold to fb_clk t htx 0 ns data_clk to data bus output delay t ddrx 0 1.2 ns data_clk to rx_frame delay t dddv 0 1.0 ns pulse width enable t enpw t cp ns txnrx t txnrxpw t cp ns fdd independent ensm mode txnrx setup to enable t txnrxsu 0 ns tdd ensm mode bus turnaround time before rx t rpre 2 t cp ns tdd mode after rx t rpst 2 t cp ns tdd mode capacitive load 3 pf capacitive input 3 pf digital data timing (lvds) data_clk clock period t cp 4.069 ns 245.76 mhz data_clk and fb_clk pulse width t mp 45% of t cp 55% of t cp ns tx data tx_frame and tx_d setup to fb_clk t stx 1 ns hold to fb_clk t htx 0 ns data_clk to data bus output delay t ddrx 0 .25 1. 2 5 ns data_clk to rx_frame delay t dddv 0 .25 1. 25 ns pulse width enable t enpw t cp ns txnrx t txnrxpw t cp ns fdd independent ensm mode txnrx setup to enable t txnrxsu 0 ns tdd ensm mode bus turnaround time before rx t rpre 2 t cp ns after rx t rpst 2 t cp ns capacitive load 3 pf capacitive input 3 pf supply characteristics 1.3 v main supply voltage 1.267 1.3 1.33 v vdd_interface supply nominal settings cmos 1.2 2.5 v lvds 1.8 2.5 v vdd_interface tolerance ?5 +5 % tolerance is applicable to any voltage setting vdd_gpo supply nominal setting 1.3 3.3 v when unused, must be set to 1.3 v vdd_gpo tolerance ?5 +5 % tolerance is applicable to any voltage setting current consumption vddx, sleep mode 180 a sum of all input currents vdd_gpo 50 a no load 1 when referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevan t to the specification is listed. for full pin names of multifunction pins, refer to the pin configuration and function descriptions section.
AD9361 data sheet rev. d | page 8 of 36 current consumption vdd_interface table 2. vdd_interface = 1.2 v parameter min typ max unit test conditions/comments sleep mode 45 a power applied, device disabled 1rx, 1tx, ddr lte10 single port 2.9 ma 30.72 mhz data clock , cmos dual port 2.7 ma 15.36 mhz data clock , cmos lte20 dual port 5.2 ma 30.72 mhz data clock , cmos 2rx, 2tx, ddr lte3 dual port 1.3 ma 7.68 mhz data clock , cmos lte10 single port 4.6 ma 61.44 mhz data clock , cmos dual port 5.0 ma 30.72 mhz data clock , cmos lte20 dual port 8.2 ma 61.44 mhz data clock , cmos gsm dual port 0.2 ma 1.08 mhz data clock , cmos wimax 8.75 dual port 3.3 ma 20 mhz data clock , cmos wimax 10 single port tdd rx 0.5 ma 22.4 mhz data clock , cmos tdd tx 3.6 ma 22.4 mhz data clock , cmos fdd 3.8 ma 44.8 mhz data clock , cmos w i max 20 dual port fdd 6.7 ma 44.8 mhz data clock , cmos table 3. vdd_interface = 1.8 v parameter min typ max unit test conditions/comments sleep mode 84 a power applied, device disabled 1rx, 1tx, ddr lte10 single port 4.5 ma 30.72 mhz data clock , cmos dual port 4.1 ma 15.36 mhz data clock , cmos lte20 dual port 8.0 ma 30.72 mhz data clock , cmos 2rx, 2tx, ddr lte3 dual port 2.0 ma 7.68 mhz data clock , cmos lte10 single port 8.0 ma 61.44 mhz data clock , cmos dual port 7.5 ma 30.72 mhz data clock , cmos lte20 dual port 14.0 ma 61.44 mhz data clock , cmos gsm dual port 0.3 ma 1.08 mhz data clock , cmos wi max 8.75 dual port 5.0 ma 20 mhz data clock , cmos
data sheet AD9361 rev. d | page 9 of 36 parameter min typ max unit test conditions/comments wimax 10 single port tdd rx 0.7 ma 22.4 mhz data clock, cmos tdd tx 5.6 ma 22.4 mhz data clock, cmos fdd 6.0 ma 44.8 mhz data clock, cmos wimax 20 dual port fdd 10.7 ma 44.8 mhz data clock, cmos p-p56 75 mv differential output 14.0 ma 240 mhz data clock, lvds 300 mv differential output 35.0 ma 240 mhz data clock, lvds 450 mv differential output 47.0 ma 240 mhz data clock, lvds table 4. vdd_interface = 2.5 v parameter min typ max unit test conditions/comments sleep mode 150 a power applied, device disabled 1rx, 1tx, ddr lte10 single port 6.5 ma 30.72 mhz data clock, cmos dual port 6.0 ma 15.36 mhz data clock, cmos lte20 dual port 11.5 ma 30.72 mhz data clock, cmos 2rx, 2tx, ddr lte3 dual port 3.0 ma 7.68 mhz data clock, cmos lte10 single port 11.5 ma 61.44 mhz data clock, cmos dual port 10.0 ma 30.72 mhz data clock, cmos lte20 dual port 20.0 ma 61.44 mhz data clock, cmos gsm dual port 0.5 ma 1.08 mhz data clock, cmos wimax 8.75 dual port 7.3 ma 20 mhz data clock, cmos wimax 10 single port tdd rx 1.3 ma 22.4 mhz data clock, cmos tdd tx 8.0 ma 22.4 mhz data clock, cmos fdd 8.7 ma 44.8 mhz data clock, cmos wimax 20 dual port fdd 15.3 ma 44.8 mhz data clock, cmos p-p56 75 mv differential output 26.0 ma 240 mhz data clock, lvds 300 mv differential output 45.0 ma 240 mhz data clock, lvds 450 mv differential output 58.0 ma 240 mhz data clock, lvds
AD9361 data sheet rev. d | page 10 of 36 current consumption vddd1p3_dig and vdda x ( c ombination of all 1. 3 v supplies) table 5. 800 mhz, tdd mode parameter min typ max unit test conditions/comments 1rx 5 mhz bandwidth 180 ma continuous rx 10 mhz bandwidth 210 ma continuous rx 20 mhz bandwidth 260 ma continuous rx 2rx 5 mhz bandwidth 265 ma continuous rx 10 mhz bandwidth 315 ma continuous rx 20 mhz bandwidth 405 ma continuous rx 1tx 5 mhz bandwidth 7 dbm 340 ma continuous tx ?27 dbm 190 ma continuous tx 10 mhz bandwidth 7 dbm 360 ma continuous tx ?27 dbm 220 ma continuous tx 20 mhz bandwidth 7 dbm 400 ma continuous tx ?27 dbm 250 ma continuous tx 2tx 5 mhz bandwidth 7 dbm 550 ma continuous tx ?27 dbm 260 ma continuous tx 10 mhz bandwidth 7 dbm 600 ma continuous tx ?27 dbm 310 ma continuous tx 20 mhz bandwidth 7 dbm 660 ma continuous tx ?27 dbm 370 ma continuous tx
data sheet AD9361 rev. d | page 11 of 36 table 6 . tdd mode , 2.4 ghz parameter min typ max unit test conditions/comments 1rx 5 mhz bandwidth 175 ma continuous rx 10 mhz bandwidth 200 ma continuous rx 20 mhz bandwidth 240 ma continuous rx 2rx 5 mhz bandwidth 260 ma continuous rx 10 mhz bandwidth 305 ma continuous rx 20 mhz bandwidth 390 ma continuous rx 1tx 5 mhz bandwidth 7 dbm 350 ma continuous tx ?27 dbm 160 ma continuous tx 10 mhz bandwidth 7 dbm 380 ma continuous tx ?27 dbm 220 ma continuous tx 20 mhz bandwidth 7 dbm 410 ma continuous tx ?27 dbm 260 ma continuous tx 2tx 5 mhz bandwidth 7 dbm 580 ma continuous tx ?27 dbm 280 ma continuous tx 10 mhz bandwidth 7 dbm 635 ma continuous tx ?27 dbm 330 ma continuous tx 20 mhz bandwidth 7 dbm 690 ma continuous tx ?27 dbm 390 ma continuous tx table 7. tdd mode, 5.5 ghz parameter min typ max unit test conditions/comments 1rx 5 mhz bandwidth 175 ma continuous rx 40 mhz bandwidth 275 ma continuous rx 2rx 5 mhz bandwidth 270 ma continuous rx 40 mhz bandwidth 445 ma continuous rx 1tx 5 mhz bandwidth 7 dbm 400 ma continuous tx ?27 dbm 240 ma continuous tx 40 mhz bandwidth 7 dbm 490 ma continuous tx ?27 dbm 385 ma continuous tx 2tx 5 mhz bandwidth 7 dbm 650 ma continuous tx ?27 dbm 335 ma continuous tx 40 mhz bandwidth 7 dbm 820 ma continuous tx ?27 dbm 500 ma continuous tx
AD9361 data sheet rev. d | page 12 of 36 table 8 . fdd mode , 800 mhz parameter min typ max unit test conditions/comments 1rx, 1tx 5 mhz bandwidth 7 dbm 490 ma ?27 dbm 345 ma 10 mhz bandwidth 7 dbm 540 ma ?27 dbm 395 ma 20 mhz bandwidth 7 dbm 615 ma ?27 dbm 470 ma 2rx, 1tx 5 mhz bandwidth 7 dbm 555 ma ?27 dbm 410 ma 10 mhz bandwidth 7 dbm 625 ma ?27 dbm 480 ma 20 mhz bandwidth 7 dbm 740 ma ?27 dbm 600 ma 1rx, 2tx 5 mhz bandwidth 7 dbm 685 ma ?27 dbm 395 ma 10 mhz bandwidth 7 dbm 755 ma ?27 dbm 465 ma 20 mhz bandwidth 7 dbm 850 ma ?27 dbm 570 ma 2rx, 2tx 5 mhz bandwidth 7 dbm 790 ma ?27 dbm 495 ma 10 mhz bandwidth 7 dbm 885 ma ?27 dbm 590 ma 20 mhz bandwidth 7 dbm 1020 ma ?27 dbm 730 ma
data sheet AD9361 rev. d | page 13 of 36 table 9 . fdd mode , 2.4 ghz parameter min typ max unit test conditions/comments 1rx, 1tx 5 mhz bandwidth 7 dbm 500 ma ?27 dbm 350 ma 10 mhz bandwidth 7 dbm 540 ma ?27 dbm 390 ma 20 mhz bandwidth 7 dbm 620 ma ?27 dbm 475 ma 2rx, 1tx 5 mhz bandwidth 7 dbm 590 ma ?27 dbm 435 ma 10 mhz bandwidth 7 dbm 660 ?27 dbm 510 ma 20 mhz bandwidth 7 dbm 770 ma ?27 dbm 620 ma 1rx, 2tx ma 5 mhz bandwidth 7 dbm 730 ma ?27 dbm 425 ma 10 mhz bandwidth 7 dbm 800 ma ?27dbm 500 ma 20 mhz bandwidth 7 dbm 900 ma ?27 dbm 600 ma 2rx, 2tx ma 5 mhz bandwidth 7 dbm 820 ?27 dbm 515 ma 10 mhz bandwidth 7 dbm 900 ma ?27 dbm 595 ma 20 mhz bandwidth 7 dbm 1050 ma ?27 dbm 740 ma
AD9361 data sheet rev. d | page 14 of 36 table 10 . fdd mode , 5.5 ghz parameter min typ max unit test conditions/comments 1rx, 1tx 5 mhz bandwidth 7 dbm 550 ma ?27 dbm 385 ma 2rx, 1tx 5 mhz bandwidth 7 dbm 645 ma ?27 dbm 480 ma 1rx, 2tx 5 mhz bandwidth 7 dbm 805 ma ?27 dbm 480 ma 2rx, 2tx 5 mhz bandwidth 7 dbm 895 ma ?27 dbm 575 ma
data sheet AD9361 rev. d | page 15 of 36 absolute maximum rat ings table 11. parameter rating vddx to vss x ? 0.3 v to + 1. 4 v vdd_interface to vss x ? 0.3 v to +3.0 v vdd_gpo to vss x ? 0.3 v to +3.9 v logic inputs and outputs to vss x ?0.3 v to vdd_interface + 0.3 v input current to any pin except supplies 10 ma rf inputs (peak power) 2.5 dbm tx monitor input power (peak power) 9 dbm package power dissipation (t jmax ? t a )/ ja maximum junction temperature (t jmax ) 110c operating temperature range ? 40c to +85c storage temperature range ? 65c to +150c reflow profile the AD9361 reflow profile is in accordance with the jedec jesd20 criteria for pb - free devices. the maximum reflow temperature is 260c. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 12 . thermal resistance package type airflow velocity (m/sec) ja 1, 2 jc 1, 3 jb 1, 4 jt 1, 2 unit 144 - ball csp _ bga 0 32.3 9.6 20.2 0.27 c/w 1.0 29.6 0.43 c/w 2.5 27.8 0.57 c/w 1 per jedec jesd 5 1 - 7, plus jedec jesd 51- 5 2s2p test board. 2 per jedec jesd51 - 2 (still air) or jedec jesd51 - 6 (moving air) . 3 per mil - s td 883, method 1012.1. 4 per jedec jesd51 - 8 (still air). esd caution s t r e s s es a b o ve t h o s e l i s t e d u n d e r a b s o l u t e m a x i m um r a t i n gs m a y c a u s e p e r m a n e n t dam a g e t o t h e d e v i c e . this is a s t r e s s r a t i n g o n l y ; fu n c t i o n a l o p e r a t i o n o f t h e d ev i c e a t t h e s e o r a n y o t h e r co n d i t i o ns a b o ve t h o s e indi c a t e d i n t h e o p e r a t i o na l s e c t i o n o f t h is s p e c i fi c a t ion is n o t i m p l i e d . e x p o su r e t o a b s o l u te ma x i m u m r a t in g c o n d i t i o n s fo r e x t e n d e d p e r i o d s m a y a ff e c t d e vi c e r e l i a b i l i t y .
AD9361 data sheet rev. d | page 16 of 36 pin configuration an d function descripti ons figure 2 . pin configuration, top view table 13 . pin function descriptions pin no. type 1 mnemonic description a1, a2 i rx2a_n, rx2a_p receive channel 2 differential i nput a. alternatively, e ach pin can be used as a single - ended input or combined to make a differential pair . tie u nused pins to ground. a3 , m3 nc nc no connect. do not connect to these pins. a4, a6, b1, b2, b12, c2, c7 to c12, f3, h2, h3, h6, j2, k2, l2, l3, l7 to l12, m4, m6 i vssa analog ground. tie these pins directly to the vssd digital ground on the printed circuit board (one ground plane). a5 i tx_mon2 t ransmit channel 2 power monitor input. if this pin is unused, tie it to ground. a7, a8 o tx2a_n, tx2a_p transmit channel 2 differential o utput a. tie u nused pins to 1.3 v. a9, a10 o tx2b_n, tx2b_p transmit channel 2 differential o utput b. tie unused pins to 1.3 v. a11 i vdda1p1_tx_vco t ransmit vco supply input. connect to b11 . a12 i tx_ext_lo_in external transmit lo input. if this pin is unused, tie it to ground. b3 o auxdac1 auxiliary dac 1 output. b4 to b7 o gpo_3 to gpo_0 3.3 v capable general - purpose outputs. b8 i vdd_gpo 2.5 v to 3.3 v supply for the auxdac and general - purpose output pins. when the vdd_gpo supply is not used, t his supply must be set to 1.3 v . b9 i vdda1p3_tx_lo transmit lo 1.3 v supply input. b10 i vdda1p3_tx_vco_ldo transmit vco ldo 1.3 v supply input. connect to b9 . b11 o tx_vco_ldo_out transmit vco ldo output. connect to a11 and a 1 f bypass capacitor in series with a 1 ? resistor to ground. c1, d1 i rx2c_p, rx2c_n receive channel 2 differential i nput c. e ach pin can be used as a single - ended input or combined to make a differential pair . these inputs experience degraded performance above 3 ghz. tie u nused pins to ground. rx2a_n rx2a_p nc vssa tx_mon2 vssa tx2a_n tx2a_p tx2b_n tx2b_p vdda1p1_ tx_vco tx_vco_ ldo_out tx_ext_ lo_in 1 2 3 4 5 6 7 8 9 10 11 12 vssa vssa auxdac1 gpo_3 gpo_2 gpo_1 gpo_0 vdd_gpo vdda1p3_ tx_lo vdda1p3_ rx_synth vdda1p3_ tx_vco_ ldo vssa rx2c_p vssa auxdac2 test/ enable ctrl_in0 ctrl_in1 vssa vssa vssa vssa vssa vssa rx2c_n vdda1p3_ rx_rf vdda1p3_ rx_tx vdda1p3_ rx_lo vdda1p3_ rx_vco_ ldo vdda1p3_ tx_lo_ buffer ctrl_out0 ctrl_in3 ctrl_in2 p0_d9/ tx_d4_p p0_d7/ tx_d3_p p0_d5/ tx_d2_p p0_d3/ tx_d1_p p0_d1/ tx_d0_p p0_d8/ tx_d4_n p0_d6/ tx_d3_n p0_d4/ tx_d2_n p0_d10/ tx_d5_n fb_clk_p fb_clk_n p0_d2/ tx_d1_n vssd rx2b_p ctrl_out1 ctrl_out2 ctrl_out3 p0_d0/ tx_d0_n p0_d11/ tx_d5_p rx2b_n vssa ctrl_out6 ctrl_out5 ctrl_out4 vssd vssd vssd vddd1p3_ dig rx_ext_ lo_in rx_vco_ ldo_out vdda1p1_ rx_vco ctrl_out7 en_agc enable rx_ frame_p rx_ frame_n tx_ frame_p data_ clk_p vssd rx1b_p vssa vssa vssa txnrx sync_in vssd p1_d11/ rx_d5_p tx_ frame_n vssd data_ clk_n vdd_ interface rx1b_n vssa spi_di spi_clk clk_out p1_d10/ rx_d5_n rx1c_p k vssa vdda1p3_ tx_synth vdda1p3_ bb resetb spi_enb p1_d8/ rx_d4_n p1_d9/ rx_d4_p p1_d6/ rx_d3_n p1_d7/ rx_d3_p p1_d4/ rx_d2_n p1_d5/ rx_d2_p p1_d2/ rx_d1_n p1_d3/ rx_d1_p p1_d0/ rx_d0_n p1_d1/ rx_d0_p vssd rx1c_n vssa vssa vssa rbias auxadc spi_do vssa vssa vssa vssa vssa rx1a_p a b c d e f g h j l m rx1a_n nc tx1b_n vssa tx_mon1 vssa tx1a_p tx1a_n tx1b_p xtalp xtaln 10453-002 analog i/o digital i/o no connect dc power ground
data sheet AD9361 rev. d | page 17 of 36 pin no. type 1 mnemonic description c3 o auxdac2 auxiliary dac 2 output. c4 i test/enable test input. ground this pin for normal operation. c5, c6, d 5 , d 6 i ctrl_in0 to ctrl_in3 control inputs. used for manual rx gain and tx attenuation control. d2 i vdda1p3_rx_rf receiver 1.3 v supply input . connect to d3 . d3 i vdda1p3_rx_tx 1.3 v supply input . d4, e4 to e6 , f4 to f6, g4 o ctrl_out0 , ctrl_out1 to ctrl_out3 , ctrl_out6 to ctrl_out4, ctrl_out7 control outputs. these pins are multipurpose outputs that have programmable functionality. d7 i/o p0_d 9/ tx_d 4_p digital data port p0 /transmit differential input bus . this is a dual function pin. as p0_d9, it functions as part of the 12- bit bidirectional parallel cmos level data p ort 0. alternatively, th is pin (tx_d4_p) can function as part of the lvds 6 - bit tx differential input bus with internal lvds termination. d8 i/o p0_d7/tx_d3_p digital data port p0/transmit differential input bus. this is a dual function pin. as p0_d7, it functions as part of the 1 2- bit bidirectional parallel cmos level data port 0. alternatively, this pin (tx_d3_p) can function as part of the lvds 6 - bit tx differential input bus with internal lvds termination. d9 i/o p0_d5/tx_d 2_ p digital data port p0/transmit differential input bus. this is a dual function pin. as p0_d5, it functions as part of the 12 - bit bidirectional parallel cmos level data port 0. alternatively, this pin (tx_d 2_p ) can function as part of the lvds 6 - bit tx differential input bus with internal lvds termination. d10 i/o p0_d3/tx_d1_p digital data port p0/transmit differential input bus. this is a dual function pin. as p0_d3, it functions as part of the 12- bit bidirectional parallel cmos level data port 0. alternatively, this pin (tx_d1_p) can function as part of the lvds 6 - bit tx differential input bus with internal lvds termination. d11 i/o p0_d1/tx_d0_p digital data port p0/transmit differential input bus. this is a dual function pin. as p0_d1, it functions as part of the 12 - bit bidirectional parallel cmos level data port 0. alternatively, this pin (tx_d0_p) can function as part of the lvds 6 - bit tx differential input bus with internal lvds termination. d12, f7, f9, f11, g12, h7, h10, k12 i vssd digital ground. tie th ese pins directly to the vssa analog ground on the printed circuit board (one ground plane). e1, f1 i rx2b_p, rx2b_n receive channel 2 differential input b. each pin can be used as a single - ended input or combined to make a differential pair . these inputs experience degraded performance above 3 ghz. tie u nused pins to ground. e2 i vdda1p3_rx_lo receive lo 1.3 v supply input. e3 i vdda1p3_tx_lo_buffer 1.3 v supply input. e7 i/o p0_d11/tx_d5_p digital data port p0/transmit differential input bus. this is a dual function pin. as p0_d11, it functions as part of the 12 - bit bidirectional parallel cmos level data port 0. alternatively, this pin (tx_d5_p) can function as part of the lvds 6- bit tx differential input bus with internal lvds termination. e8 i/o p0_ d8/tx_d4_n digital data port p0/transmit differential input bus. this is a dual function pin. as p0_d8, it functions as part of the 12 - bit bidirectional parallel cmos level data port 0. alternatively, this pin (tx_d4_n) can function as part of the lvds 6 - bit tx differential input bus with internal lvds termination. e9 i/o p0_d6/tx_d3_n digital data port p0/transmit differential input bus. this is a dual function pin. as p0_d6, it functions as part of the 12- bit bidirectional parallel cmos level data por t 0. alternatively, this pin (tx_d3_n) can function as part of the lvds 6 - bit tx differential input bus with internal lvds termination. e10 i/o p0_d4/tx_d2_n digital data port p0/transmit differential input bus. this is a dual function pin. as p0_d4, it f unctions as part of the 12 - bit bidirectional parallel cmos level data port 0. alternatively, this pin (tx_d2_n) can function as part of the lvds 6 - bit tx differential input bus with internal lvds termination. e11 i/o p0_d2/tx_d1_n digital data port p0/transmit differential input bus. this is a dual function pin. as p0_d2, it functions as part of the 12 - bit bidirectional parallel cmos level data port 0. alternatively, this pin (tx_d1_n) can function as part of the lvds 6 - bit tx differential input bus with internal lvds termination. e12 i/o p0_d0/tx_d0_n digital data port p0/transmit differential input bus. this is a dual function pin. as p0_d0, it functions as part of the 12 - bit bidirectional parallel cmos level data port 0. alternatively, this pin (t x_d0_n) can function as part of the lvds 6 - bit tx differential input bus with internal lvds termination.
AD9361 data sheet rev. d | page 18 of 36 pin no. type 1 mnemonic description f2 i vdda1p3_rx_vco_ldo receive vco ldo 1.3 v s upply input . connect to e2. f8 i/o p0_d10/tx_d5_n digital data port p0/transmit differential input bus. this is a dual function pin. as p0_d10, it functions as part of the 12 - bit bidirectional parallel cmos level data port 0. alternatively, this pin (tx_d5_n) can function as part of the lvds 6- bit tx differential input bus with internal lvds termination . f10, g10 i fb_clk_p, fb_clk_n feedback clock. these pins receive the fb_clk signal that clock s in tx data. in cmos mode, use fb_clk_p as the input and tie fb_clk_n to ground . f12 i vddd1p3_dig 1.3 v digital supply input . g1 i rx_ext_lo_in external receive lo input. if this pin is unused, tie it to ground. g2 o rx_vco_ldo_out receive vco ldo output. connect this pin directly to g3 and a 1 f bypass capacitor in series with a 1 ? resistor to ground. g3 i vdda1p1_rx_vco receive vco supply input. conn ect this pin directly to g2 only . g5 i en_agc manual control input for automatic gain control ( agc ) . g6 i enable control input. this pin move s the device through various operational states. g7, g8 o rx_frame_n, rx_frame_p r eceive digital data framing output signal. th ese pin s transmit the rx_frame signal that ind icate s whether the rx output data is valid. in cmos mode, use rx_frame_p as the output and leave rx_frame_n unconnected. g9, h9 i tx_frame_p, tx_frame_n t ransmit digital data framing input signal. these pins receive the tx_frame signal that indicates when tx data is valid. in cmos mode, use tx_frame_p as the input and tie tx_frame_n to ground. g11, h11 o data_clk_p, data_clk_n receive data clock output. these pins transmit the data_clk signal that is used by the bbp to clock rx data. in cmos mode, use data_clk_p as the output and leave data_clk_n unconnected. h1, j1 i rx1b_p, rx1b_n r eceive channel 1 differential input b. alternatively , e ach pin can be used as a single - ended input . these inputs experience degraded performance above 3 ghz. tie u nused pins to ground. h4 i txnrx enable state machine control signal. this pin control s the data port bus direction. logic low selects the rx direction , and logic high selects the tx direction. h5 i sync_in input to synchronize digital clocks between multiple AD9361 devices. if this pin is unused, tied it to ground . h8 i/o p1_d11 / rx_d5 _p digital data port p1/receive differential out put bus. this is a dual function pin. as p1_d1 1 , it functions as part of the 12 - bit bidirectional parallel cmos level data port 1 . alternatively, this pin (rx_d5_ p ) can function as part of the lvds 6- bit rx dif ferential out put bus with internal lvds termination. h12 i vdd_interface 1.2 v to 2.5 v supply for digital i/o pins (1.8 v to 2.5 v in lvds mode). j3 i vdda1p3_rx_synth 1.3 v supply input . j4 i spi_di spi serial data input. j5 i spi_clk spi clock input. j6 o clk_out output clock. this pin c an be configured to output either a buffered version of the external input clock , the dcxo, or a divided - down version of the internal adc_clk. j7 i/o p1_d10/rx_d5_n digital data port p1/receive differential output bus. this is a dual function pin. as p1_d10, it functions as part of the 12 - bit bidirectional parallel cmos level data port 1 . alternatively, this pin ( r x_d 5 _n) can function as part of the lvds 6- bit r x differential output bus with internal lvds ter mination. j8 i/o p1_d9/rx_d4_p digital data port p1/receive differential output bus. this is a dual function pin. as p1_d9, it functions as part of the 12 - bit bidirectional parallel cmos level data port 1 . alternatively, this pin (rx_d4_p) can function as part of the lvds 6 - bit rx differential output bus with internal lvds termination. j9 i/o p1_d7/rx_d3_p digital data port p1/receive differential output bus. this is a dual function pin. as p1_d7, it functions as part of the 12 - bit bidirectional parallel cmos level data port 1 . alternatively, this pin (rx_d3_p) can function as part of the lvds 6 - bit rx differential output bus with internal lvds terminatio n. j10 i/o p1_d5/rx_d2_p digital data port p1/receive differential output bus. this is a dual function pin. as p1_d5, it functions as part of the 12 - bit bidirectional parallel cmos level data port 1 . alternatively, this pin (rx_d2_p) can function as part of the lvds 6 - bit rx differential output bus with internal lvds termination.
data sheet AD9361 rev. d | page 19 of 36 pin no. type 1 mnemonic description j11 i/o p1_d3/rx_d1_p digital data port p1/receive differential output bus. this is a dual function pin. as p1_d3, it functions as part of the 12 - bit bidirectional parallel cmos level data port 1 . alternatively, this pin (rx_d1_p) can function as part of the lvds 6 - bit rx differential output bus with internal lvds termination. j12 i/o p1_d1/rx_d0_p digital data port p1/receive differential output bus. this is a dual function pin. as p1_d1, it functions as part of the 12 - bit bidirectional parallel cmos level data port 1 . alternatively, this pin (rx_d0_p) can function as part of the lvds 6 - bit rx differential output bus with internal lvds terminatio n. k1, l1 i rx1c_p, rx1c_n r eceive channel 1 differential input c. alternatively, e ach pin can b e used as a single - ended input. these inputs experience degraded performance above 3 ghz. tie u nused pins to ground. k3 i vdda1p3_tx_synth 1.3 v supply input . k4 i vdda1p3_bb 1.3 v supply input. k5 i resetb asynchronous reset. logic low resets the device. k6 i spi_enb spi enable input . set this pin to logic low to enable the spi bus. k7 i/o p1_d8/rx_d4_n digital data port p1/receive differential output bus. this is a dual function pin. as p1_d8, it functions as part of the 12 - bit bidirectional parallel cmos level data port 1 . alternatively, this pin (rx_d4_n) can function as part of the lvds 6 - bit rx differential output bus with internal lvds terminatio n. k8 i/o p1_d6/rx_d3_n digital data port p1/receive differential output bus. this is a dual function pin. as p1_d 6 , it functions as part of the 12 - bit bidirectional parallel cmos level data port 1 . alternatively, this pin (rx_d 3_n ) can function as part of the lvds 6 - bit rx differential output bus with internal lvds termination. k9 i/o p1_d 4 /rx_d 2_n digital data port p1/receive differential output bus. this is a dual function pin. as p1_d 4 , it functions as part of the 12 - bit bidirectional parallel cmos level data port 1 . alternatively, this pin (rx_d 2_n ) can function as part of the lvds 6 - bit rx differential output bus with internal lvds termination. k10 i/o p1_d 2 /rx_d 1_n digital data port p1/receive differential out put bus. this is a dual function pin. as p1_d 2 , it functions as part of the 12 - bit bidirectional parallel cmos level data port 1 . alternatively, this pin (rx_d 1_n ) can function as part of the lvds 6 - bit rx differential output bus with internal lvds term ination. k11 i/o p1_d 0 /rx_d 0_n digital data port p1/receive differential output bus. this is a dual function pin. as p1_d 0 , it functions as part of the 12 - bit bidirectional parallel cmos level data port 1 . alternatively, this pin (rx_d0_ n ) can function as part of the lvds 6 - bit rx differential output bus with internal lvds termination. l4 i rbias bias input reference. connect this pin through a 14.3 k ? (1% tolerance) resistor to ground. l5 i auxadc auxiliary adc input. if this pin is unused, tie it to ground. l6 o spi_do spi serial data output in 4 - wire mode, or high - z in 3 - wire mode. m1, m2 i rx1a_p, rx1a_n r eceive channel 1 differential input a. alternatively , each pin can be used as a single - ended input. tie u nused pins to ground. m5 i tx_mon1 t ransmit channel 1 power monitor input. when this pin is unused, tie it to ground. m7, m8 o tx1a_p, tx1a_n transmit channel 1 differential output a. tie u nused pins to 1.3 v. m9, m10 o tx1b_p, tx1b_n transmit channel 1 differential output b. tie unused pins to 1.3 v. m11, m12 i xtalp, xtaln reference frequency crystal connections. when a crystal is used, connect it between these two pins. when an external clock source is used, connect it to xtaln and leave xtalp unconn ected. 1 i is input, o is output, i/o is input/output, or nc is not connected.
AD9361 data sheet rev. d | page 20 of 36 typical performance characteristics 800 mh z frequency band figure 3 . rx noise figure vs. rf frequency figure 4 . rssi error vs. rx input powe r, lte 10 mhz modulation (referenced to ? 5 0 dbm input power at 800 mhz ) figure 5 . rssi error vs. rx input power, e dge modulation (referenced to ?5 0 dbm input power at 800 mhz) figure 6 . rx evm vs. rx input power , 64 qam lte 10 mhz mode, 19.2 mhz ref_clk figure 7 . rx evm vs. rx input power, gsm mode, 30.72 mhz ref_clk (doubled internally for rf synthesizer) figure 8 . rx evm vs. interferer power level , lte 10 mhz signal of interest with p in = ?82 dbm, 5 mhz ofdm blocker at 7.5 mhz offset 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 700 750 800 850 900 rx noise figure (db) rf frequency (mhz) ?40c +25c +85c 10453-003 ?3 ?2 ?1 0 1 2 3 4 5 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 rssi error (db) rx input power (dbm) ?40c +25c +85c 10453-004 ?3 ?2 ?1 0 1 2 3 ? 1 10 ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 rssi error (db) rx input power (dbm) ?40c +25c +85c 10453-005 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 rx evm (db) rx input power (dbm) ?40c +25c +85c 10453-006 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 rx evm (db) rx input power (dbm) ?40c +25c +85c 10453-007 ?30 ?25 ?20 ?15 ?10 ?5 0 ? 72 ? 68 ? 64 ? 60 ? 56 ? 52 ? 48 ? 44 ? 40 ? 36 ? 32 rx evm (db) interferer power leve l (dbm) ?40c +25c +85c 10453-008
data sheet AD9361 rev. d | page 21 of 36 figure 9 . rx evm vs. interferer power level , lte 10 mhz signal of interest with p in = ?90 dbm, 5 mhz ofdm blocker at 17.5 mhz offset figure 10 . rx noise figure vs. interferer power level , e dge signal of interest with p in = ?90 dbm, cw blocker at 3 mhz offse t, gain index = 64 figure 11 . rx gain vs. rx lo frequency, gain index = 76 (maximum setting) figure 12 . third - order input intercept point (iip3) vs. rx gain index, f1 = 1.45 mhz, f2 = 2.89 mhz, gsm mode figure 13 . second - order input intercept point (iip2) vs. rx gain index, f1 = 2.00 mhz, f2 = 2.01 mhz, gsm mode figure 14 . rx local oscillator (lo) leakage vs. rx lo frequency ?16 ?12 ?8 ?4 0 ?56 ?54 ?52 ?50 ?48 ?46 ?44 ?42 ?40 ?38 ?36 rx evm (db) interferer power level (dbm) ?40c +25c +85c 10453-009 0 2 4 6 8 10 12 14 ?47 ?43 ?39 ?35 ?31 ?27 ?23 rx noise figure (db) interferer power level (dbm) ?40c +25c +85c 10453-010 66 68 70 72 74 76 78 80 700 750 800 850 900 rx gain (db) rx lo frequenc y (mhz) ?40c +25c +85c 10453-0 1 1 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 20 28 36 44 52 60 68 76 iip3 (dbm) ?40c +25c +85c rx gain index 10453-012 0 10 20 30 40 50 60 70 80 90 100 20 28 36 44 52 60 68 76 iip2 (dbm) rx gain index ?40c +25c +85c 10453-013 ?130 ?125 ?120 ?115 ?110 ?105 ?100 700 750 800 850 900 rx lo leakage (dbm) rx lo frequency (mhz) ?40c +25c +85c 10453-014
AD9361 data sheet rev. d | page 22 of 36 figure 15 . rx emission at lna input, dc to 12 ghz, f lo_rx = 800 mhz, lte 10 mhz, f lo_tx = 860 mhz figure 16 . tx output power vs. tx lo frequency, attenuation setting = 0 db, single tone output figure 17 . tx power control linearity error vs. attenuation setting figure 18 . tx spectrum vs. frequency offset from carrier frequency, f lo_tx = 800 mhz, lte 10 mhz downlink (digital attenuation variations shown) figure 19. tx spectrum vs. frequency offset from carrier frequency, f lo_tx = 800 mhz, gsm downlink (digital attenuation variations shown), 3 mhz range figure 20. tx spectrum vs. frequency offset from carrier frequency, f lo_tx = 800 mhz, gsm downlink (digital attenuation variations shown), 12 mhz range ?120 ?100 ?80 ?60 ?40 ?20 0 0 2000 4000 6000 8000 10000 12000 power a t ln a input (dbm/750khz) frequenc y (mhz) 10453-015 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 700 750 800 850 900 tx output power (dbm) tx lo frequency (mhz) ?40c +25c +85c 10453-016 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 10 20 30 40 50 ste p linearit y error (db) a ttenu a tion setting (db) ?40c +25c +85c 10453-017 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?15 ?10 ?5 0 5 10 15 transmitter output power (dbm/100khz) frequenc y offset (mhz) att 0db att 3db att 6db 10453-018 ?100 ?80 ?60 ?40 ?20 0 20 transmitter output power (dbm/30khz) frequenc y offset (mhz) a tt 0 d b a tt 3 d b a tt 6 d b 10453-019 ?1.6 ?1.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ?120 ?100 ?80 ?60 ?40 ?20 0 20 ?6 ?4 ?2 0 2 4 6 transmitter output power (dbm/30khz) frequenc y offset (mhz) a tt 0 d b a tt 3 d b a tt 6 d b 10453-020
data sheet AD9361 rev. d | page 23 of 36 figure 21 . tx evm vs. t x attenuation setting, f lo_tx = 800 mhz, lte 10 mhz, 64 qam modulation, 19.2 mhz ref_clk figure 22 . tx evm vs. tx attenuation setting, f lo_tx = 800 mhz, gsm modulation , 30.72 mhz ref_clk (doubled internally for rf synthesizer) figure 23 . integrated tx lo phase noise vs. frequency, 19.2 mhz ref_clk figure 24 . integrated tx lo phase noise vs. frequency, 30.72 mhz ref_clk (doubled internally for rf synthesizer ) figure 25 . tx carrier rejection vs. frequency figure 26 . tx second - order harmonic distortion (hd2) vs. frequency ?50 ?45 ?40 ?35 ?30 ?25 ?20 0 5 10 15 20 25 30 35 40 tx evm (db) tx attenuation setting (db) ?40c +25c +85c 10453-021 ?50 ?45 ?40 ?35 ?30 ?25 ?20 0 10 20 30 40 50 tx evm (db) tx attenuation setting (db) ?40c +25c +85c 10453-022 0 0.1 0.2 0.3 0.4 0.5 700 750 800 850 900 integr a ted phase noise (rms) frequenc y (mhz) ?40c +25c +85c 10453-023 0 0.05 0.10 0.15 0.20 0.25 0.30 700 750 800 850 900 integr a ted phase noise (rms) frequenc y (mhz) ?40c +25c +85c 10453-024 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 700 750 800 850 900 tx carrier amplitude (dbc) frequenc y (mhz) att 0, ?40c att 25, ?40c att 50, ?40c att 0, +25c att 25, +25c att 50, +25c att 0, +85c att 25, +85c att 50, +85c 10453-025 ?80 ?75 ?70 ?65 ?60 ?55 ?50 700 750 800 850 900 tx second- order harmonic distortion (dbc) frequency (mhz) att 0, ?40c att 25, ?40c att 50, ?40c att 0, +25c att 25, +25c att 50, +25c att 0, +85c att 25, +85c att 50, +85c 10453-026
AD9361 data sheet rev. d | page 24 of 36 figure 27 . tx third - order harmonic distortion (hd3) vs. frequency figure 28 . tx third - order output intercept point (oip3) vs. tx attenuation setting figure 29 . tx signal - to - noise ratio (snr) vs. t x attenuation setting, lte 10 mhz signal of interest with noise measured at 90 mhz offset figure 30 . tx signal - to - noise ratio (snr) vs. t x attenuation setting, gsm signal of interest with noise measured at 20 mhz offset figure 31 . tx single sideband (ssb) rejection vs. freq uency, 1.5375 m hz offset ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 700 750 800 850 900 tx third-order harmonic distortion (dbc) frequency (mhz) att 0, ?40c att 25, ?40c att 50, ?40c att 0, +25c att 25, +25c att 50, +25c att 0, +85c att 25, +85c att 50, +85c 10453-027 0 5 10 15 20 25 30 0 4 8 12 16 20 tx oip3 (dbm) tx attenuation setting (db) ?40c +25c +85c 10453-028 140 145 150 155 160 165 170 0 3 6 9 12 15 tx snr (db/hz) tx a ttenu a tion setting (db) ?40c +25c +85c 10453-029 140 145 150 155 160 165 170 0 4 8 12 16 20 tx snr (db/hz) tx a ttenu a tion setting (db) ?40c +25c +85c 10453-030 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 700 750 800 850 900 tx single sideband amplitude (dbc) frequency (mhz) att 0, ?40c att 25, ?40c att 50, ?40c att 0, +25c att 25, +25c att 50, +25c att 0, +85c att 25, +85c att 50, +85c 10453-031
data sheet AD9361 rev. d | page 25 of 36 2.4 gh z frequency band figure 32 . rx noise figure vs. rf frequency figure 33 . rssi error vs. rx input power , referenced to ? 5 0 dbm input power at 2.4 g hz figure 34 . rx evm vs. input power , 64 qam lte 20 mhz mode, 40 mhz ref_clk figure 35 . rx evm vs. interferer power level , lte 20 mhz signal of interest with p in = ?75 dbm, lte 20 mhz blocker at 20 mhz offset figure 36 . rx evm vs. interferer power level , lte 20 mhz signal of interest with p in = ?75 dbm, lte 20 mhz blocker at 40 mhz offset figure 37 . rx gain vs. rx lo frequency, gain index = 76 (maximum setting) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 rx noise figure (db) rf frequency (mhz) ?40c +25c +85c 10453-032 ?3 ?2 ?1 0 1 2 3 4 5 ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 rssi error (db) rx input power (dbm) ?40c +25c +85c 10453-033 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 rx evm (db) input power (dbm) ?40c +25c +85c 10453-034 ?30 ?25 ?20 ?15 ?10 ?5 0 ?72 ?68 ?64 ?60 ?56 ?52 ?48 ?44 ?40 ?36 ?32 ?28 rx evm (db) interferer power leve l (dbm) ?40c +25c +85c 10453-035 ?30 ?25 ?20 ?15 ?10 ?5 0 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 rx evm (db) interferer power leve l (dbm) ?40c +25c +85c 10453-036 66 68 70 72 74 76 78 80 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 rx gain (db) rx lo frequenc y (mhz) ?40c +25c +85c 10453-037
AD9361 data sheet rev. d | page 26 of 36 figure 38 . third - order input intercept point (iip3) vs. rx gain index, f1 = 30 mhz, f2 = 61 mhz figure 39 . second - order input inter cept point (iip2) vs. rx gain index, f1 = 60 mhz, f2 = 61 mhz figure 40 . rx local oscillator (lo) leakage vs. rx lo frequency figure 41 . rx emission at lna input, dc to 12 ghz, f lo_rx = 2.4 ghz, lte 20 mhz, f lo_tx = 2.46 ghz figure 42 . tx output power vs. tx lo frequency, attenuation setting = 0 db, single tone output figure 43 . tx power control linearity error vs. attenuation setting ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 20 28 36 44 52 60 68 76 iip3 (dbm) rx gain index ?40c +25c +85c 10453-038 20 30 40 50 60 70 80 20 28 36 44 52 60 68 76 iip2 (dbm) rx gain index ?40c +25c +85c 10453-039 ?130 ?125 ?120 ?115 ?110 ?105 ?100 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 rx lo leakage (dbm) rx lo frequency (mhz) ?40c +25c +85c 10453-040 ?120 ?100 ?80 ?60 ?40 ?20 0 0 2000 4000 6000 8000 10000 12000 power a t ln a input (dbm/750khz) frequenc y (mhz) 10453-041 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 tx output power (dbm) tx lo frequenc y (mhz) ?40c +25c +85c 10453-042 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 10 20 30 40 50 ste p linearit y error (db) a ttenu a tion setting (db) ?40c +25c +85c 10453-043
data sheet AD9361 rev. d | page 27 of 36 figure 44 . tx spectrum vs. frequency offset from carrier frequency, f lo_tx = 2.3 ghz, lte 20 mhz downlink (digital attenuation variations shown) figure 45 . tx evm vs. transmitter attenuation settin g, 40 mhz ref_clk, lte 20 mhz, 64 qam modulation figure 46 . integrated tx lo phase noise vs. frequency, 40 mhz ref_clk figure 47 . tx carrier rejection vs. frequency figure 48 . tx second - order harmonic distortion (hd2) vs. frequency figure 49 . tx third - order harmonic distortion (hd3) vs. frequency ?120 ?100 ?80 ?60 ?40 ?20 0 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 transmitter output power (dbm/100khz) frequenc y offset (mhz) att 0db att 3db att6db 10453-044 ?50 ?45 ?40 ?35 ?30 ?25 ?20 0 5 10 15 20 25 30 35 40 tx evm (db) a ttenu a tion setting (db) ?40c +25c +85c 10453-045 0 0.1 0.2 0.3 0.4 0.5 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 integr a ted phase noise (rms) frequenc y (mhz) ?40c +25c +85c 10453-046 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 tx carrier amplitude (dbc) frequenc y (mhz) att 0, ?40c att 25, ?40c att 50, ?40c att 0, +25c att 25, +25c att 50, +25c att 0, +85c att 25, +85c att 50, +85c 10453-047 ?80 ?75 ?70 ?65 ?60 ?55 ?50 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 tx second-order harmonic distortion (dbc) frequency (mhz) att 0, ?40c att 25, ?40c att 50, ?40c att 0, +25c att 25, +25c att 50, +25c att 0, +85c att 25, +85c att 50, +85c 10453-048 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 tx third-order harmonic distortion (dbc) frequency (mhz) att 0, ?40c att 25, ?40c att 50, ?40c att 0, +25c att 25, +25c att 50, +25c att 0, +85c att 25, +85c att 50, +85c 10453-049
AD9361 data sheet rev. d | page 28 of 36 figure 50 . tx third - order output intercept point (oip3) vs. tx attenuation setting figure 51 . tx signal - to - noise ratio (snr) vs. t x attenuation setting, lte 20 mhz signal of interest with noise measured at 90 mhz offset figure 52 . tx single sideband (ssb) rejection vs. frequency, 3.075 mhz offset 0 5 10 15 20 25 30 0 4 8 12 16 20 tx oip3 (dbm) tx attenuation setting (db) ?40c +25c +85c 10453-050 140 142 144 146 148 150 152 154 156 158 160 0 3 6 9 12 15 tx snr (db/hz) tx a ttenu a tion setting (db) ?40c +25c +85c 10453-051 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 tx single sideband amplitude (dbc) frequency (mhz) att 0, ?40c att 25, ?40c att 50, ?40c att 0, +25c att 25, +25c att 50, +25c att 0, +85c att 25, +85c att 50, +85c 10453-052
data sheet AD9361 rev. d | page 29 of 36 5.5 gh z frequency band figure 53 . rx noise figure vs. rf frequency figure 54 . rssi error vs. rx input power, referenced to ?5 0 dbm input power at 5.8 g hz figure 55 . rx evm vs. rx input power, 64 qam wimax 40 mhz mode, 40 mhz ref_clk (doubled internally for rf synthesizer) figure 56 . rx evm vs. interferer power level , wimax 40 mhz signal of interest with p in = ?7 4 dbm, wimax 40 mhz blocker at 40 mhz offset figure 57 . rx evm vs. interferer power level , wimax 40 mhz signal of interest with p in = ?7 4 dbm, wimax 4 0 mhz blocker at 8 0 mhz offset figure 58 . rx gain vs. frequency, gain index = 76 (maximum setting) 0 1 2 3 4 5 6 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 rx noise figure (db) rf frequency (ghz) ?40c +25c +85c 10453-053 ?3 ?2 ?1 0 1 2 3 4 5 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 rssi error (db) rx input power (dbm) ?40c +25c +85c 10453-054 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 ?74 ?68 ?62 ?56 ?50 ?44 ?38 ?32 ?26 ?20 rx evm (db) rx input power (dbm) ?40c +25c +85c 10453-055 ?25 ?20 ?15 ?10 ?5 0 5 ?72 ?67 ?62 ?57 ?52 ?47 ?42 ?37 ?32 rx evm (db) interferer power leve l (dbm) ?40c +25c +85c 10453-056 ?25 ?20 ?15 ?10 ?5 0 5 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 rx evm (db) interferer power leve l (dbm) ?40c +25c +85c 10453-057 60 62 64 66 68 70 rx gain (db) ?40c +25c +85c 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 frequenc y (ghz) 10453-058
AD9361 data sheet rev. d | page 30 of 36 figure 59 . third - order input intercept point (iip3) vs. rx gain index, f1 = 5 0 mhz, f2 = 10 1 mhz figure 60 . second - order input intercept point (iip2) vs. rx gain index, f1 = 7 0 mhz, f2 = 7 1 mhz figure 61 . rx local oscillator (lo) leakage vs. frequency figure 62 . rx emission at lna input, dc to 26 ghz, f lo_rx = 5.8 ghz, wimax 40 mhz figure 63 . tx output power vs. frequency, attenuation setting = 0 db, single tone figure 64 . tx power control linearity error vs. attenuation setting ?20 ?15 ?10 ?5 0 5 10 15 20 6 16 26 36 46 56 66 76 iip3 (dbm) rx gain index ?40c +25c +85c 10453-059 20 30 40 50 60 70 80 20 28 36 44 52 60 68 76 iip2 (dbm) rx gain index 10453-060 ?40c +25c +85c ?110 ?108 ?106 ?104 ?102 ?100 ?98 ?96 ?94 ?92 ?90 rx lo leakage (dbm) 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 frequency (ghz) ?40c +25c +85c 10453-061 ?120 ?100 ?80 ?60 ?40 ?20 0 0 5 10 15 20 25 30 power a t ln a input (dbm/150khz) frequenc y (ghz) 10453-062 4 5 6 7 8 9 10 5.0 5.1 5.2 5.3 5.4 5.5. 5.6 5.7 5.8 5.9 6.0 tx output power (dbm) frequenc y (ghz) ?40c +25c +85c 10453-063 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 10 20 30 40 50 60 70 80 90 ste p linearit y error (db) a ttenu a tion setting (db) ?40c +25c +85c 10453-064
data sheet AD9361 rev. d | page 31 of 36 figure 65 . tx spectrum vs. frequency offset from carrier frequency, f lo_tx = 5.8 ghz, wimax 4 0 mhz downlink (digital attenuation variations shown) figure 66 . tx evm vs. t x attenuation setting, wimax 40 mhz, 64 qam modulation , f lo_tx = 5.495 ghz, 40 mhz ref_clk (doubled internally for rf synthesizer ) figure 67 . integrated tx lo phase noise vs. frequency, 40 mhz ref_clk (doubled internally for rf synthesizer) figure 68 . tx carrier rejection vs. frequency figure 69 . tx second - order harmonic distortion (hd2) vs. frequency figure 70 . tx third - order harmonic distortion (hd3) vs. frequency ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 transmitter output power (dbm/1mhz) frequenc y offset (mhz) a tt 0 d b a tt 3 d b a tt 6 d b 10453-065 ?40 ?38 ?36 ?34 ?32 ?30 0 2 4 6 8 10 tx evm (db) tx attenuation setting (db) ?40c +25c +85c 10453-066 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 integr a ted phase noise (rms) 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 frequenc y (ghz) ?40c +25c +85c 10453-067 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 tx carrier amplitude (dbc) 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 frequenc y (ghz) 10453-068 att 0, ?40c att 25, ?40c att 50, ?40c att 0, +25c att 25, +25c att 50, +25c att 0, +85c att 25, +85c att 50, +85c ?80 ?75 ?70 ?65 ?60 ?55 ?50 tx second-order harmonic distortion (dbc) 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 frequency (ghz) 10453-069 att 0, ?40c att 25, ?40c att 50, ?40c att 0, +25c att 25, +25c att 50, +25c att 0, +85c att 25, +85c att 50, +85c ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 tx third-order harmonic distortion (dbc) 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 frequency (ghz) 10453-070 att 0, ?40c att 25, ?40c att 50, ?40c att 0, +25c att 25, +25c att 50, +25c att 0, +85c att 25, +85c att 50, +85c
AD9361 data sheet rev. d | page 32 of 36 figure 71 . tx third - order output intercept point (oip3) vs. tx attenuation setting , f lo_tx = 5.8 ghz figure 72 . tx signal - to - noise ratio (snr) vs. t x attenuation setting, wimax 40 mhz signal of interest wit h noise measured at 90 mhz offset , f lo_tx = 5.745 ghz figure 73 . tx single sideband (ssb) rejection vs. frequency, 7 mhz offset ?4 0 4 8 12 16 20 0 4 8 12 16 20 tx oip3 (dbm) tx attenuation setting (db) ?40c +25c +85c 10453-071 142 143 144 145 146 147 148 149 150 0 3 6 9 12 15 tx snr (db/hz) tx a ttenu a tion setting (db) ?40c +25c +85c 10453-072 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 tx single sideband amplitude (dbc) 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 frequency (ghz) 10453-073 att 0, ?40c att 25, ?40c att 50, ?40c att 0, +25c att 25, +25c att 50, +25c att 0, +85c att 25, +85c att 50, +85c
data sheet AD9361 rev. d | page 33 of 36 theory of operation general the AD9361 is a highly integrated radio frequency (rf) transceiver capable of being configured for a wide range of applications. the device integrates all rf, mixed signal, and digital blocks necessary to provide all transceiver functions in a single de vice. programmability allows this broadband transceiver to be adapted for use with multiple communication standards, including frequency division duplex (fdd) and time division duplex (tdd) systems. this p rogrammability also allows the device to be interfaced to various baseband processors (bbps) using a single 12 - bit parallel data port, dual 12 - bit parallel data ports, or a 12- bit low voltage differential signaling (lvds) interface. the AD9361 also provides self - calibration and automatic gain control (agc) systems to maintain a high performance level under varying temperatures and input signal conditions. in addition, the device includes several te st modes that allow system designers t o insert test tones and create internal loopback modes that can be used by designers to debug their designs during prototyping and optimize their radio configuration for a specific application. receiver the receiver s ection contains all blocks necessary to receive rf signals and convert them to digital data that is usable by a bbp. there are two independently controlled channels that can receive signals from different sources, allowing the device to be used in multi ple input, multi ple output (mimo) systems while sharing a common frequency synthesizer. each channel has three inputs that can be multiplexed to the signal chain, making the AD9361 suitable for use in diversity systems with multiple antenna inputs. the receiver is a direct conversion system that contains a low noise amplifier (lna), followed by matched in - phase (i) and quadrature (q) amplifiers , mixers, and band shaping filters that down convert rece ived signals to baseband for digitization. external lnas can also be interfaced to the device, allowing designers the flexibility to customize the receiver front end for their specific application. gain control is achieved by following a preprogrammed gain index map that distributes gain among the blocks for optim al performance at each level. this can be achieved by enabling the internal agc in either fast or slow mode or by using manual gain control, allowing the bbp to make the gain adjustments as needed. additionally, each channel contains independent rssi measurement capability, dc offset tracking, and all circuitry necessary for self - calibration . the receivers include 12 - bit , sigma - delta ( - ) adcs and adjustable sample rates that produce data streams from the received signals. the digitized signals can be conditioned further by a series of decimation filters and a fully programmable 128 - tap fir filter with additional decimation se ttings. the sample rate of each digital filter block is adjustable by cha nging decimation factors to produce the desired output data rate. transmitter the transmitter section consists of two identical and independently controlled channels that provide all digital processing, mixed signal, and rf blocks necessary to implement a direct conversion system while sharing a common frequency synthesizer. the digital data received from the bbp passe s through a fully programmable 128- tap fir filter with interpolation options. the fir output is sent to a series of interpolation filters tha t provide additional filtering and data rate interpolation prior to reaching the dac. each 12 - bit dac has an adjustable sampling rate. both the i and q channels are fed to the rf block for upconversion. when converted to baseband analog signals, the i and q signals are filtered to remove sampling artifacts and fed to the upconversion mixers. at this point, the i and q signals are recombined and modulated on the carrier frequency for transmission to the output stage. the combined signal also pass es through analog filters that provide additional band shaping , and then the signal is transmitted to the output amplifier. each transmit channel provid es a wide attenuation adjustment range with fine granularity to help designers optimize signal - to - noise ra tio (snr). self - calibration circuitry is built into each transmit channel to provide automatic real - time adjustment. the transmitter block also provides a tx monitor block for each channel. this block monitors the transmitter output and routes it back through an unused receiver channel to the bbp for signal monitoring. the tx monitor blocks are available only in tdd mode operation while the receiver is idle. clock input options the AD9361 oper ates using a reference clock that can be provided by two different sources. the first option is to use a dedicated cryst al with a frequency between 19 mhz and 50 mhz connected between the xtalp and xtal n pins. the second option is to connect an external os cillator or clock distribution devic e (such as the ad9548 ) to the xtaln pin (with the xtal p pin remaining unconnected). if an external oscillator is used, the frequency can vary between 1 0 mhz and 80 mhz. this reference clock is used to supply the synthesizer blocks that generate all data clocks, sample clocks, and local oscillators inside the device. errors in the crystal frequency can be removed by using the digitally programmable digitall y controlled crystal oscillator ( dcxo ) function to adjust the on - chip variable capacitor. this capacitor can tune the crystal frequency variance out of the system, resulting in a more accurate reference clock from which all other frequency signals are gene rated. this function can also be used with on - chip temperature sensing to provide oscillator frequency temperature compensation during normal operation.
AD9361 data sheet rev. d | page 34 of 36 synthesizers rf plls the AD9361 contains tw o identical synthesizers to generate the required l o signals for the rf signal paths : one for the receiver and one fo r the transmitter. p hase - locked loop (pll) synthesizer s are fractional - n designs incorporating completely integrated voltage controlled oscillators (vcos) and loop filters. in tdd op eration, the synthesizers turn on and off as appropriate for the rx and tx frames. in fdd mode, the tx pll and the rx pll can be activated simultaneously . these plls re quire no external components. bb pll the AD9361 also contains a baseband pll synthesizer that is used to generate all baseband related clock signals. these include the adc and dac sampling clocks , the data_clk signal (see the digital data interface section), and all data framing signals. this pll is programmed from 700 mhz to 1400 mhz based on the data rate and sample rate requirements of t he system. digital data interfa ce the AD9361 data interface uses parallel data ports (p0 and p1) to transfer data between the dev ice and the bbp. the data ports can be configured in either single - ended cmos format or differential lvds format. both formats can be configured in multiple arrangements to match system requirements for data ordering and data port connections. these arrang ements include single port data bus, dual port data bus, single data rate, double data rate, and various combinations of data ordering to transmit data from different channels across the bus at appropriate times. bus transfers are controlled using simple h ardware handshake signaling. the two por ts can be operated in either bi directional (tdd) mode or in full duplex (fdd) mode where half the bits a re used for transmitting data and half are used for receiving data . the interface can also be configured to use only one of the data ports for applications that do not require high data rates and prefer to use fewer interface pins. data_clk signal rx data supplies the data_clk signal that the bbp can use when receiving the data. the data_clk can be set to a rate that provides single data rate (sdr) timing where data is sampled o n each rising clock edge , or it can be set to provide double data r ate (ddr) timing where data is captured on both rising and falling edges. this timing applies to operation usin g either a single port or both ports. fb_clk signal for transmit data, the interface uses the fb_clk signal as the timing reference. fb_clk allows source synchronous timing with rising edge capture for burst control signals and either rising edge (sdr mod e) or both edge capture (ddr mode) for transmit signal bursts. the fb_clk signal must have the same frequency and duty cycle as data_clk. rx_frame signal th e device generates an rx_frame output signal whenever the receiver outputs valid data. this signal h as two modes: level mode (rx_frame stays high as long as the data is valid) and pulse mo de (rx_frame pulses with a 50% duty cycle). similarly, the bbp must provide a tx_frame signal that indicates the beginn ing of a valid data transmission with a rising ed ge. similar to the rx_frame, th e tx_frame signal can remain high throughout the burst or it can be pulsed with a 50% duty cycle. enable state machine the AD9361 transceiver includes an enable state ma chine (ensm) that allows real - time control over the current state of the device. the device ca n be placed in several different states dur ing normal operation, including ? wa it power save, synthesizers disabled ? s leep w ait with all clocks/bb pll disabled ? tx tx signal chain enabled ? rx rx signal chain enabled ? fdd tx and rx signal chains enabled ? alert synthesizers enabled the ensm has two possible control methods : spi control and pin control. spi control mode in spi control mode, the ensm is control led asynchronously by writing spi registers to advance the current state to the next state. spi control is considered asynchronous to the data_clk because the spi_clk can be derived from a different clock reference and can still function properly. the spi control ensm method is recommended when real - time control of the synthesizers is not necessary. spi control can be used for real - time control as long as the bbic has the ability to perform timed spi writes accurately . pin control mode in pin control mode , the enable function of the enable pin and the txnrx pin allow real - time control of the current state. the ensm allows tdd or fdd operation depending on the configuration of the corresponding spi register. the enable and txnrx pin control method is recomm ended if the bbic has extra control outputs that can be controlled in real time, allowing a simple 2 - wire interface to control the state of the device. to advance the current state of the ensm to the next state, the enable function of the enable pin can be driven by either a pulse (edge detected internally) or a level. when a pulse is used, it must have a minimum pulse width of one fb_clk cycle . in level mode, the enable and txnrx pins are also edge detected by the AD9361 and must meet the same minimum pulse width requirement of one fb_clk cycle.
data sheet AD9361 rev. d | page 35 of 36 in fdd mode, the enable and txnrx pins can be remapped to serve as real - time rx and tx data transfer control sig nals. in this mode, the enable pin enables or disables the receive signal path, and the txnrx pin enables or disables the transmit signal path. in this mode, the ensm is removed from the system for control of all data flow by these pins. spi interface the AD9361 uses a serial peripheral inte rface (spi) to communicate with the bbp. this interface can be configured as a 4 - wire interface with dedicated receive and transmit ports, or it can be configu red as a 3 - wire interface with a bi direction al data communication port. this bus allows the bbp to set all device control parameters using a simple address data serial bus protocol. write commands follow a 24 - bit format. the first six bits are used to set the bus direction and number of bytes to transfer. the next 10 bits set the address where data is to be written. the final eight bits are the data to be transferred to the specifie d register address (msb to lsb). the AD9361 also supports an lsb - first format that allows the commands to be written in lsb to msb format. in this mode, the register addr esses are incre mented for multi byte writes. read commands follow a similar format with the ex cept ion that the first 16 bits are transferred on the spi_di pin and the final eight bits are read from the AD9361 , either on the spi_do pin in 4 - wire mode or on the spi_di pin in 3 - wire mode. co ntrol pins control outputs (ctrl_out[7:0]) the AD9361 provides eight simultaneous real - time output signals for use as interrupts to the bbp. these outputs can be configured to output a number of internal settings and mea surements that the bbp can use when monitoring transceiver performance in different situations. the control output pointer register selects what information is output to these pins, and the control output ena ble register determines which signals are activated for monitoring by the bbp. signals used for manual gain mode, calibration flags, state machine states, and the adc output are among the outputs that can be monitored on these pins. control inputs (ctrl_ in[3:0]) the AD9361 provides four edge detected control input pins . in manual gain mode, the bbp can use these pins to change the gain table index in real time. in transmit mode, the bbp can use t wo of the pins to change the transmit gain in real time. gpo pins (gpo _ 3 to gpo_ 0 ) the AD9361 provides four , 3.3 v capable general - purpose logic output pins: gpo_3, gpo_2, gpo_1, and gpo_0. these pins c an be used to control other peripheral devices such as regulators and switches via the AD9361 spi bus , or they can function as slave s f or the internal AD9361 state machine. a uxiliary converters auxadc the AD9361 contains an auxiliary adc that can be used to monitor system functions such as temperature or power output. the converter is 12 bits wide and has an input range of 0 v to 1.25 v. when enabled, the adc is free running. spi reads provide the last value latched at the adc output. a multiplexer in front of the adc allows the user to select between the auxadc input p in and a built - in temperature sensor. auxdac1 and auxdac2 the AD9361 contains two identical auxiliary dacs that can provide power amplifier (pa) bias or other system functionality. t he auxiliary d acs are 10 bits wide, have an ou tput voltage range of 0.5 v to vdd_gpo ? 0.3 v, a current drive of 10 ma, and can be directly controlled by the internal enable state machine. powering the AD9361 t he AD9361 must be powered by the following t hree supplies : the analog supply ( vddd1p3_dig/vddax = 1.3 v), the interface supply (vdd_interface = 1.8 v), and the gpo supply ( vdd_gpo = 3.3 v). for ap plications requiring optimal noise performance, it is recommended that the 1.3 v analog supply be s plit and sourced from low noise, low dropout ( ldo ) regulator s. figure 74 shows th e recommended method. figure 74 . low n oise power solution for the AD9361 for applications where board space is at a premium, and optimal noise performance is not an absolute requirement, the 1.3 v analog rail can be provided directly from a switcher , and a more integrated power management unit ( pmu ) approach can be adopted. figure 75 shows this approach. figure 75 . space - optimized power solution for the AD9361 10453-074 3.3v 1.8v 1.3v_a 1.3v_b adp2164 adp1755 adp1755 10453-075 adp1755 ldo adp5040 1.2a buck 300ma ldo 300ma ldo AD9361 1.3v vddd1p3_dig/vddax 1.8v vdd_interface 3.3v vdd_gpo
AD9361 data sheet rev. d | page 36 of 36 packaging and orderi ng info rmation outline dimensions figure 76 . 144 - ball chip scale package ball grid array [csp_bga] (bc - 144 - 7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD9361 bbcz ? 40 c to +85 c 144- ball chip scale package ball grid array [csp_bga] bc -144-7 AD9361 bbcz -r eel ? 40c to +85c 144- ball chip scale package ball grid array [csp_bga] bc -144-7 1 z = rohs compliant part. compliant to jedec standards mo-275-eeab-1. 1 1-18-20 1 1- a 0.80 0.60 ref a b c d e f g 9 10 8 11 12 7 5 6 4 2 3 1 bottom view 8.80 sq h j k l m detail a top view detail a coplanarity 0.12 0.50 0.45 0.40 1.70 max ball diameter seating plane 10.10 10.00 sq 9.90 a1 ball corner a1 ball corner 0.32 min 1.00 min ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10453 - 0- 11/13(d)

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